Development of a pattern-matching algorithm for the ATLAS Level-zero muon trigger.

The ATLAS Level-0 muon trigger for the High-Luminosity LHC upgrade will use powerful Field-Programmable Gate Arrays (FPGAs) to perform fast trigger algorithms. In particular, the Barrel Sector Logic board will receive hit data from the RPC detectors and the Tile Calorimeter and should provide muon candidates within a latency of few hundreds of nanoseconds. Different approaches can be used to implement the trigger algorithms in the FPGA firmware: geometrical methods, neural networks, pattern matching. We discuss the development and optimization of pattern matching algorithms and we compare them to other approaches.