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Dislocation density evolution in PVT growth of 150 and 200 mm SiC.
Ellison A., Sundqvist B., Sörman E., Lilja L., Lima L.M.C., Paradiso D., Westberg N., Hult P., Riva L., Carria E., Gritti A., Bergman P., Magnusson B.
In order to support a rapid adoption of energy efficient SiC power devices in e.g. automotive applications, it is valuable to minimize, in a cost-effective way, the density of dislocations that can reduce the device yield and reliability. A certain percentage of Threading Screw Dislocations (TSD) could reduce the reliability of MOSFETs when they produce a surface nano-pit in the active epilayer. Basal Plane Dislocations (BPD) are well known to induce degradation of bipolar devices, such as a body diode. In this study, we describe the evolution of the density of Threading Edge Dislocations (TED), BPDs and TSDs (pure and mixed) along the growth direction in SiC bulk crystals. 150mm 4H-SiC n-type wafers $(4^\circ$ off-axis) were manufactured from ingots grown by a PVT method developed at STM Sweden. The dislocation density was measured on the Si-face by KOH etching two wafers per ingot, one close to the start, and one close to the end of the growth. For TSD mapping, low n-doped epilayers were grown prior to etching, so that TSDs (pure or mixed) could reliably be identified by their larger etch pit area than TEDs, based on an earlier correlation with X-ray topography. For BPD mapping, the recognition of the shell-shape of the etch pits was used after etching the Si-face of bare n+ substrates. In an optimized PVT process, the selection of the seed is of key importance towards lowering TSD and BPD-TED densities, and this has allowed the crystal growth expansion to 200mm wafers.